IJSRD - International Journal for Scientific Research & Development| Vol. 1, Issue 10, 2013 | ISSN (online): 2321-0613
نویسندگان
چکیده
a proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S-box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.
منابع مشابه
IJSRD - International Journal for Scientific Research & Development| Vol. 2, Issue 07, 2014 | ISSN (online): 2321-0613
This paper investigated the performance of Mary DPSK on Rayleigh Channel on the basis of Bit Error Rate (BER). BER is calculated by using simulation of system model consisting of source, modulator, channel and demodulator on MATLAB platform.
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متن کاملIJSRD - International Journal for Scientific Research & Development| Vol. 4, Issue 03, 2016 | ISSN (online): 2321-0613
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متن کاملIJSRD - International Journal for Scientific Research & Development| Vol. 4, Issue 10, 2016 | ISSN (online): 2321-0613
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متن کاملIJSRD - International Journal for Scientific Research & Development| Vol. 4, Issue 02, 2016 | ISSN (online): 2321-0613
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متن کاملIJSRD - International Journal for Scientific Research & Development| Vol. 4, Issue 04, 2016 | ISSN (online): 2321-0613
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